The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, conventional gate cutting techniques are significantly constrained by the dense packing of IC features required for advanced IC technology nodes. In particular, gate cutting techniques typically implement etching processes that completely (or substantially) remove an entire portion of a gate stack (including, for example, at least one gate electrode layer and at least one gate dielectric layer). However, it has been observed that lateral etching arising from these etching processes can damage surrounding features of the ICs, such as the source/drain features. Accordingly, although existing gate cutting techniques and resulting gate structures have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.